The performance of a processor is, in part, dependent upon how efficient the processor's instruction set architecture performs in an intended application program. By evaluating the processor's use in the intended application program, areas for improvement in the processor's instruction set are many times recognized. With a processor already being used in an existing product or application, extending the processor's instruction set to address recognized areas for improvement, for example, providing additional instruction types, support of additional data types, support for increased capacity register files, and improved conditional execution capabilities, is a difficult problem. This problem is due to the need to maintain support of the original instruction set architecture while providing super-set instruction capabilities and to the limited room for growth usually available in the original instructions' formats. An attempt to address such issues was described in an IBM Technical Disclosure Bulletin (TDB) titled “Selecting Predecoded Instructions with a Surrogate”, dated August, 1992.
The “Selecting Predecoded Instructions with a Surrogate” TDB, dated August, 1992, describes the idea of storing predecoded (no instruction decode required) instructions in a special on-chip predecoded instruction memory (PDIM) and selecting individual predecoded instructions to be executed by use of “surrogate” instructions placed in the native instruction stream. The particular processor architecture for which this idea was originally proposed was a processor utilizing a 3-stage pipeline. That pipeline posed implementation problems in executing the surrogate instruction which, as part of its execution, caused a predecoded instruction to be fetched from the PDIM and then executed in place of the surrogate instruction. One of the implementation problems concerned situations requiring that a data memory effective address (EA) be resolved for a predecoded instruction selected for execution. The solution described in the TDB article involved including a component of the effective address in a field in the surrogate instruction itself. This was done so that the surrogate provided address component could be used in a simplified address resolution process during the decode stage of the surrogate instruction while the pre-decoded instruction was being accessed from the PDIM. In the TDB article, the address component included in the surrogate instruction was illustrated to be 16-bits out of a 32-bit surrogate instruction format. The TDB article also indicated the instruction to be decoded and stored in decoded form in the PDIM could be a compound instruction. A compound instruction is typically one in which two instructions are compressed into a single instruction format while specifying operations of the two instructions under specific rules governed by the compressed instruction format. For example, a specific rule may be a reduced register file address space for accessing operands, or having the same target register address for both operations.
The use of 16-bits, half of the available surrogate 32-bit instruction format, for address generation purposes, poses a severe restriction on defining the surrogate instruction. If the 16-bit address component was not required in the surrogate instruction, these 16-bits could be used for other purposes. Also, due to the limited 16-bit space remaining in the surrogate instruction, it is difficult to include additional control information such as the type of effective address generation required, further limiting the usefulness of this approach. The surrogate definition problem becomes even more difficult depending upon the number of address resolutions required by the pre-decoded instruction. Consider a surrogate compound instruction requiring address resolutions to support a memory load operation and a memory store operation, both operations to be simultaneously executed when selected by the single surrogate instruction. As specified by the TDB, the load and store operations would require the surrogate instruction to provide address components for both the load and store operations. The specification of two address components in a single 32-bit surrogate instruction is a difficult task to adequately support within a constrained space such as 16-bits for most typical processors and their associated memory subsystems.
A further problem concerns the memory space required to store predecoded instructions according to the approach of the TDB. For example, consider the storage requirements for a PDIM in a hypothetical 32-bit instruction processor. A predecoded 32-bit instruction would require extensive storage, in most typical cases. For example, predecoding a 6-bit opcode and a 4 dbit data type field would require 64-bits and 16-bits, respectively. Without any further predecoding, storage space for 80 predecoded bits and 22 instruction bits would be required. Since full decoding was required by the TDB article, greater than 102 bits would generally be required for a predecoded 32-bit instruction. With K predecoded instructions, a memory of Kx(>192-bits) would be needed and may not be justifiable given the chip area required to implement. As can be seen, there are a number of difficulties presented by the prior art TDB.